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IEICE Trans

Keyword : multi-chip structure

Hierarchical Multi-Chip Architecture for High Capacity Scalability of Fully Parallel Hamming-Distance Associative Memories
Yusuke OIKE Makoto IKEDA Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/11/01
Vol. E87-C  No. 11 ; pp. 1847-1855
Type of Manuscript:  Special Section PAPER (Special Section on New System Paradigms for Integrated Electronics)
Category: 
Keyword: 
associative memory, content addressable memory, CAM, Hamming distance, capacity scalability, multi-chip structure, 
 Summary | Full Text:PDF