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IEICE Trans

Keyword : massively parallel processor

Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture
Toru SHIMIZU Masami NAKAJIMA Masahiro KAINAGA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2006/11/01
Vol. E89-C  No. 11 ; pp. 1512-1518
Type of Manuscript:  INVITED PAPER (Special Section on Novel Device Architectures and System Integration Technologies)
Category: 
Keyword: 
massively parallel processor, SIMD, fine-grained ALU, wideband bus, 
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