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IEICE Trans

Keyword : low bit resolution

Low-Power VLSI Architecture for a New Block-Matching Motion Estimation Algorithm Using Dual-Bit-Resolution Images
Wujian ZHANG Runde ZHOU Tsunehachi ISHITANI Ryota KASAI Toshio KONDO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2001/03/01
Vol. E84-C  No. 3 ; pp. 399-409
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
motion estimation, low bit resolution, VLSI architecture, parallelism, low power, 
 Summary | Full Text:PDF