Quick Delay Calculation Model for Logic Circuit Optimization in Early Stages of LSI Design Norio OHKUBOTakeo YAMASHITA
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2003/04/01 Vol. E86-CNo. 4 ;
pp. 618-623 Type of Manuscript: Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies) Category: Design Methods and Implementation Keyword: delay calculation, effective capacitance, logic circuit optimization, delay optimization, LSI design,