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IEICE Trans

Keyword : junction capacitance

Power Reduction of New Divided Layer Bitline Dual Port SRAM with a-Si/Ti Local Wiring Scheme
Koichi MORIKAWA Jiro IDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/12/25
Vol. E79-C  No. 12 ; pp. 1713-1719
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Power LSI Technologies)
Category: 
Keyword: 
local wiring, junction capacitance, embedded SRAM, coupling noise, 
 Summary | Full Text:PDF