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IEICE Trans

Keyword : interconnection problem

Implementation of a DRAM-Cell-Based Multiple-Valued Logic-in-Memory Circuit
Hiromitsu KIMURA Takahiro HANYU Michitaka KAMEYAMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2002/10/01
Vol. E85-C  No. 10 ; pp. 1814-1823
Type of Manuscript:  PAPER
Category: Optoelectronics
Keyword: 
interconnection problem, pass-transistor network, functional pass gate, multiple-valued logic, content-addressable memory, 
 Summary | Full Text:PDF