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IEICE Trans

Keyword : high-performance

Small-Area CNN Inference Architecture with Bit-Serial Pipeline Datapath and Zero Skipping
Shinya HATTORI Hiroyuki OCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2026/03/01
Vol. E109-A  No. 3 ; pp. 552-562
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
bit-serial arithmetic unit, pipeline processing, convolutional neural network, rectified linear unit, high-performance, and area-efficient, 
 Summary | Full Text:PDF
Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing
Koki ISHIDA Masamitsu TANAKA Takatsugu ONO Koji INOUE 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2018/05/01
Vol. E101-C  No. 5 ; pp. 359-369
Type of Manuscript:  INVITED PAPER (Special Section on Innovative Superconducting Devices Based on New Physical Phenomena)
Category: 
Keyword: 
single flux quantum (SFQ), cryogenic computing, microprocessor, cache memory, Josephson junction, low-power, high-performance, energy-efficient, 
 Summary | Full Text:PDF