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IEICE Trans

Keyword : high density SRAM

A 4-Mb SRAM Using a New Hierarchical Bit Line Organization Utilizing a T-Shaped Bit Line for a Small Sized Die
Yoshiyuki HARAGUCHI Toshihiko HIROSE Motomu UKITA Tomohisa WADA Masanao EINO Minoru SAITO Michihiro YAMADA Akihiko YASUOKA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1996/06/25
Vol. E79-C  No. 6 ; pp. 743-749
Type of Manuscript:  Special Section PAPER (Special Issue on ULSI Memory Technology)
Category: Static RAMs
Keyword: 
integrated electronics, high density SRAM, hierarchical bit line organization, T-shaged bit line, 
 Summary | Full Text:PDF