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IEICE Trans

Keyword : false-triggering immunity

Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness
Yuan WANG Guangyi LU Yize WANG Xing ZHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2017/03/01
Vol. E100-C  No. 3 ; pp. 344-347
Type of Manuscript:  BRIEF PAPER
Category: Semiconductor Materials and Devices
Keyword: 
electrostatic discharge (ESD), robustness, false-triggering immunity, transmission-line-pulsing (TLP) test, 
 Summary | Full Text:PDF