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IEICE Trans

Keyword : embedded processor and low power instruction cache design

A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache
Gi-Ho PARK Jung-Wook PARK Hoi-Jin LEE Gunok JUNG Sung-Bae PARK Shin-Dug KIM 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2009/04/01
Vol. E92-C  No. 4 ; pp. 517-521
Type of Manuscript:  Special Section LETTER (Special Section on Low-Leakage, Low-Voltage, Low-Power and High-Speed Technologies for System LSIs in Deep-Submicron Era)
Category: 
Keyword: 
way-enabling mechanism, branch information, embedded processor and low power instruction cache design, 
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