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IEICE Trans

Keyword : double buffer structure

A 100 MHz 7.84 mm2 31.7 msec 439 mW 512-Point 2-Dimensional FFT Single-Chip Processor
Naoto MIYAMOTO Leo KARNAN Kazuyuki MARUO Koji KOTANI Tadahiro OHMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2004/04/01
Vol. E87-C  No. 4 ; pp. 502-509
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power System LSI, IP and Related Technologies)
Category: 
Keyword: 
fast Fourier transform, cached-memory architecture, double buffer structure, 
 Summary | Full Text:PDF