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IEICE Trans

Keyword : digital circuits

A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic
Tomoyuki TANAKA Christopher L. AYALA Nobuyuki YOSHIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2022/06/01
Vol. E105-C  No. 6 ; pp. 270-276
Type of Manuscript:  Special Section PAPER (Special Section on Progress & Trend of Superconductor-based Computers)
Category: 
Keyword: 
superconductor logic circuit, adiabatic quantum-flux-parametron, Kogge-Stone adder, superconductor electronics, digital circuits, 
 Summary | Full Text:PDF
Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique
Yuji OSAKI Tetsuya HIROSE Kei MATSUMOTO Nobutaka KUROKI Masahiro NUMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/01/01
Vol. E94-C  No. 1 ; pp. 80-88
Type of Manuscript:  PAPER
Category: Electronic Circuits
Keyword: 
subthreshold operation, digital circuits, PVT variation, delay compensation, 
 Summary | Full Text:PDF
An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs
Yusuke TSUGITA Ken UENO Tetsuya HIROSE Tetsuya ASAI Yoshihito AMEMIYA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2010/06/01
Vol. E93-C  No. 6 ; pp. 835-841
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuits and Related SoC Integration Technologies)
Category: 
Keyword: 
digital circuits, threshold voltage variation, compensation circuit, PVT variation, 
 Summary | Full Text:PDF
Opposite-Phase Clock Tree for Peak Current Reduction
Yow-Tyng NIEH Shih-Hsu HUANG Sheng-Yu HSU 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A  No. 12 ; pp. 2727-2735
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Synthesis
Keyword: 
clocks, design methodology, digital circuits, 
 Summary | Full Text:PDF
FPGA Implementation of a Digital Chaos Circuit Realizing a 3-Dimensional Chaos Model
Kei EGUCHI Takahiro INOUE Akio TSUNEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6 ; pp. 1176-1178
Type of Manuscript:  Special Section LETTER (Special Section of Papers Selected from ITC-CSCC'97)
Category: Nonlinear Problems
Keyword: 
chaos circuits, discrete-time circuits, digital circuits, integrated circuits,  FPGA implementation, 
 Summary | Full Text:PDF
Design of a Digital Chaos Circuit with Nonlinear Mapping Function Learning Ability
Kei EGUCHI Takahiro INOUE Akio TSUNEDA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1998/06/25
Vol. E81-A  No. 6 ; pp. 1223-1230
Type of Manuscript:  PAPER
Category: Nonlinear Problems
Keyword: 
chaos circuits, neuro-fuzzy circuits, supervised learning, discrete-time circuits, digital circuits, integrated circuits, 
 Summary | Full Text:PDF
Design of a Two-Dimensional Digital Chaos Circuit Realizing a Henon Map
Kei EGUCHI Takahiro INOUE Akio TSUNEDA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/01/25
Vol. E81-C  No. 1 ; pp. 78-81
Type of Manuscript:  LETTER
Category: Electronic Circuits
Keyword: 
chaos circuits, digital circuits, discrete-time circuits, integrated circuits, FPGA, 
 Summary | Full Text:PDF
Monolithic Integration of Resonant Tunneling Diode and HEMT for Low-Voltage, Low-Power Digital Circuits
Yuu WATANABE Yasuhiro NAKASHA Kenji IMANISHI Masahiko TAKIKAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1995/04/25
Vol. E78-C  No. 4 ; pp. 368-373
Type of Manuscript:  Special Section PAPER (Special Issue on Low-Voltage, Low-Power Integrated Circuits)
Category: Device Technology
Keyword: 
RTD, HEMT, SRAM, negative differential resistance, digital circuits, 
 Summary | Full Text:PDF