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IEICE Trans

Keyword : data inversion register

A Line-Mode Test with Data Register for ULSI Memory Architecture
Tsukasa OOISHI Masaki TSUKUDE Kazutani ARIMOTO Yoshio MATSUDA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1595-1603
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
line-mode test, data inversion register, main-sub I/O line architecture, 
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