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IEICE Trans

Keyword : critical area analysis

Layout-Aware Fast Bridge/Open Test Generation by 2-Step Pattern Reordering
Masayuki ARAI Shingo INUYAMA Kazuhiko IWASAKI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2018/12/01
Vol. E101-A  No. 12 ; pp. 2262-2270
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
weighted fault coverage, critical area, critical area analysis, bridge fault, open fault, 
 Summary | Full Text:PDF
A New Critical Area Simulation Algorithm and Its Application for Failing Bit Analysis
Chizu MATSUMOTO Yuichi HAMAMURA Yoshiyuki TSUNODA Hiroshi UOZAKI Isao MIYAZAKI Shiro KAMOHARA Yoshiyuki KANEKO Kenji KANAMITSU 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/03/01
Vol. E94-C  No. 3 ; pp. 353-360
Type of Manuscript:  PAPER
Category: Semiconductor Materials and Devices
Keyword: 
defects, failure analysis, fail bit signature, critical area analysis, integrated circuit layout, 
 Summary | Full Text:PDF