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IEICE Trans

Keyword : clock multiplier

A Jitter Suppression Technique for a Clock Multiplier
Kiyoshi ISHII Keiji KISHINE Haruhiko ICHINO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2000/04/25
Vol. E83-C  No. 4 ; pp. 647-651
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
clock multiplier, phase-locked loop, SAW filter, jitter generation, jitter transfer function, 
 Summary | Full Text:PDF