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IEICE Trans

Keyword : boost logic

An Energy Efficiency 4-bit Multiplier with Two-Phase Non-overlap Clock Driven Charge Recovery Logic
Yimeng ZHANG Leona OKAMURA Tsutomu YOSHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/04/01
Vol. E94-C  No. 4 ; pp. 605-612
Type of Manuscript:  Special Section PAPER (Special Section on Circuits and Design Techniques for Advanced Large Scale Integration)
Category: 
Keyword: 
adiabatic logic, boost logic, low energy dissipation, pipeline multiplier, 
 Summary | Full Text:PDF