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IEICE Trans

Keyword : bitonic sorter three-valued distributed coding

Design of Robust-Fault-Tolerant Multiple-Valued Arithmetic Circuits and Their Evaluation
Takeshi KASUGA Michitaka KAMEYAMA Tatsuo HIGUCHI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/03/25
Vol. E76-C  No. 3 ; pp. 428-435
Type of Manuscript:  Special Section PAPER (Special Issue on Multiple-Valued Integrated Circuits)
Category: 
Keyword: 
robust-fault-tolerant arithmetic circuit, bitonic sorter three-valued distributed coding, safety, scaler multiple-valued current-mode circuit, 
 Summary | Full Text:PDF