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IEICE Trans

Keyword : bitline capacitance

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications
Nobutaro SHIBATA Yoshinori GOTOH Takako ISHIHARA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2016/06/01
Vol. E99-C  No. 6 ; pp. 717-726
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
10T type, bitline capacitance, CMOS, gate array, high speed, low power, memory-oriented base cell, shared contact, two-port SRAM, 
 Summary | Full Text:PDF