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IEICE Trans

Keyword : area and power efficient fully-parallel LDPC decoder

Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms
Qi WANG Kazunori SHIMIZU Takeshi IKENAGA Satoshi GOTO 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/10/01
Vol. E90-C  No. 10 ; pp. 1964-1971
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
Category: VLSI Architecture for Communication/Server Systems
Keyword: 
area and power efficient fully-parallel LDPC decoder, improved simplified min-sum algorithms, power-saved strategy, 
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