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ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits
Yuya USHIODA Mineo KANEKO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2024/03/01
Vol. E107-A
No. 3 ;
pp. 600-609
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: VLSI Design Technology and CAD
Keyword:
adiabatic logic, 2LAL, optimization, decompute operation, | | | Summary | Full Text:PDF | |
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Recent Progress on Reversible Quantum-Flux-Parametron for Superconductor Reversible Computing
Naoki TAKEUCHI Yuki YAMANASHI Nobuyuki YOSHIKAWA | Publication: IEICE TRANSACTIONS on Electronics
Publication Date: 2018/05/01
Vol. E101-C
No. 5 ;
pp. 352-358
Type of Manuscript:
INVITED PAPER (Special Section on Innovative Superconducting Devices Based on New Physical Phenomena)
Category:
Keyword:
reversible computing, adiabatic logic, QFP, | | | Summary | Full Text:PDF | |
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A Lower-Power Register File Based on Complementary Pass-Transistor Adiabatic Logic
Jianping HU Tiefeng XU Hong LI | Publication: IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D
No. 7 ;
pp. 1479-1485
Type of Manuscript:
Special Section PAPER (Special Section on Recent Advances in Circuits and Systems--Part 1)
Category: Digital Circuits and Computer Arithmetic
Keyword:
register file, low power, adiabatic logic, VLSI design, | | | Summary | Full Text:PDF | |
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4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic