Ka-Band Stacked-FET Power Amplifier IC with Adaptively Controlled Gate Capacitor and Two-Step Adaptive Bias Circuit in 45-nm SOI CMOS Tsuyoshi SUGIURAToshihiko YOSHIMASU
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2023/07/01 Vol. E106-CNo. 7 ;
pp. 382-390 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Keyword: power amplifier, stacked-FET, adaptive bias, adaptive gate capacitor, SOI CMOS,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2021/02/01 Vol. E104-ANo. 2 ;
pp. 477-483 Type of Manuscript: INVITED PAPER (Special Section on Analog Circuit Techniques and Related Topics) Category: Keyword: high back-off efficiency, stacked-FET, adaptive bias, adaptive load, CMOS SOI,
Publication: IEICE TRANSACTIONS on Electronics Publication Date: 2020/04/01 Vol. E103-CNo. 4 ;
pp. 153-160 Type of Manuscript: Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology) Category: Microwaves, Millimeter-Waves Keyword: adaptive bias, high back-off efficiency, high linearity, SOI CMOS,