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IEICE Trans

Keyword : a parallel structured architecture

Power Optimization for Data Compressors Based on a Window Detector in a 5454 Bit Multiplier
Minkyu SONG Kunihiro ASADA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1997/07/25
Vol. E80-C  No. 7 ; pp. 1016-1024
Type of Manuscript:  PAPER
Category: Integrated Electronics
Keyword: 
a parallel structured architecture, low power data compressors, a Window Detector, 
 Summary | Full Text:PDF