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IEICE Trans

Keyword : ULSI memory

A Smart Design Methodology with Distributed Extra Gate-Arrays for Advanced ULSI Memories
Masaki TSUKUDA Kazutami ARIMOTO Mikio ASAKURA Hideto HIDAKA Kazuyasu FUJISHIMA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1993/11/25
Vol. E76-C  No. 11 ; pp. 1589-1594
Type of Manuscript:  Special Section PAPER (Special Issue on LSI Memories)
Category: DRAM
Keyword: 
reduction of design TAT, design methodology, ULSI memory, 
 Summary | Full Text:PDF