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IEICE Trans

Keyword : RDAC

A 7GS/s Complete-DDFS-Solution in 65nm CMOS
Abdel MARTINEZ ALONSO Masaya MIYAHARA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2018/04/01
Vol. E101-C  No. 4 ; pp. 206-217
Type of Manuscript:  Special Section PAPER (Special Section on Solid-State Circuit Design — Architecture, Circuit, Device and Design Methodology)
Category: 
Keyword: 
complete-DDFS-solution, high-speed DDFS, CMOS, RDAC, RSTC-DEM, rail-to-rail operation, two-times interleaved, 
 Summary | Full Text:PDF
Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell
Mitsutoshi SUGAWARA Kenji MORI Zule XU Masaya MIYAHARA Kenichi OKADA Akira MATSUZAWA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2016/12/01
Vol. E99-A  No. 12 ; pp. 2435-2443
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
analog synthesis, RDAC, slice-based layout, SKILL language, 
 Summary | Full Text:PDF