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IEICE Trans

Keyword : Delay/Skew variation

Robust Buffered Clock Tree Synthesis by Sensitivity Based Link Insertion
Joon-Sung YANG Ik Joon CHANG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2013/01/01
Vol. E96-C  No. 1 ; pp. 127-131
Type of Manuscript:  BRIEF PAPER
Category: Electronic Circuits
Keyword: 
clock network synthesis, link Insertion, Delay/Skew variation, Monte Carlo simulation, 
 Summary | Full Text:PDF