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IEICE Trans

Keyword : CMOS VLSI processor

Programmable Power Management Architecture for Power Reduction
Tohru ISHIHARA Hiroto YASUURA 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 1998/09/25
Vol. E81-C  No. 9 ; pp. 1473-1480
Type of Manuscript:  Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
Category: 
Keyword: 
low power design, power management, CMOS VLSI processor, 
 Summary | Full Text:PDF