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IEICE Trans

Keyword : Bipolar-CMOS-DMOS process

A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 µm Bipolar-CMOS-DMOS Process
Jae-Young PARK Dae-Woo KIM Young-Sang SON Jong-Kyu SONG Chang-Soo JANG Won-Young JUNG 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2011/05/01
Vol. E94-C  No. 5 ; pp. 796-801
Type of Manuscript:  Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)
Category: 
Keyword: 
electrostatic discharge (ESD), non-snapback characteristics, gate-coupled effect, isolated parasitic capacitance, Bipolar-CMOS-DMOS process, 
 Summary | Full Text:PDF