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IEICE Trans

Keyword : 1R/1W-SRAM

A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses
Hiroyuki YAMAUCHI Toshikazu SUZUKI Yoshinobu YAMAGAMI 
Publication:   IEICE TRANSACTIONS on Electronics
Publication Date: 2007/04/01
Vol. E90-C  No. 4 ; pp. 749-757
Type of Manuscript:  Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Memory
Keyword: 
SRAM, 1R/1W-SRAM, disturbed access, SNM, write margin, cell current, 
 Summary | Full Text:PDF