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IEICE Trans

Keyword : wirability

An Incremental Wiring Algorithm for VLSI Layout Design
Yukiko KUBO Shigetoshi NAKATAKE Yoji KAJITANI Masahiro KAWAKITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2003/05/01
Vol. E86-A  No. 5 ; pp. 1203-1206
Type of Manuscript:  Special Section LETTER (Special Section on Discrete Mathematics and Its Applications)
Category: 
Keyword: 
wirability, incremental wiring, channel intersection graph, wire decomposition, 
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