Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A
No. 12 ;
pp. 3238-3247
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Embedded, Real-Time and Reconfigurable Systems
Keyword:
two-level cache, L1/L2, cache optimization, design space exploration, cache simulation, embedded system, |