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IEICE Trans

Keyword : topology selection and sizing

Find the 'Best' Solution from Multiple Analog Topologies via Pareto-Optimality
Yu LIU Masato YOSHIOKA Katsumi HOMMA Toshiyuki SHIBUYA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2009/12/01
Vol. E92-A  No. 12 ; pp. 3035-3043
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Device and Circuit Modeling and Analysis
Keyword: 
analog design, topology selection and sizing, automation, multi-objective optimization, Pareto-optimality, 
 Summary | Full Text:PDF