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IEICE Trans

Keyword : timing error correction

A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm
Keisuke OKUNO Shintaro IZUMI Kana MASAKI Hiroshi KAWAGUCHI Masahiko YOSHIMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2015/12/01
Vol. E98-A  No. 12 ; pp. 2592-2599
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Circuit Design
Keyword: 
ADPLL, fast settling, digital calibration, timing error correction, temperature compensation, 
 Summary | Full Text:PDF