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IEICE Trans

Keyword : timed circuits

Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation
Tomoya KITAI Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/11/01
Vol. E88-D  No. 11 ; pp. 2555-2564
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
trace theoretic verification, failure analysis, timed circuits, timing constraints, 
 Summary | Full Text:PDF
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits
Denduang PRADUBSUWUN Tomohiro YONEDA Chris MYERS 
Publication:   IEICE TRANSACTIONS on Information and Systems
Publication Date: 2005/07/01
Vol. E88-D  No. 7 ; pp. 1646-1661
Type of Manuscript:  PAPER
Category: Dependable Computing
Keyword: 
timed trace theory, timed circuits, formal verification, safety/timing failures, 
 Summary | Full Text:PDF
Modular Synthesis of Timed Circuits Using Partial Order Reduction
Tomohiro YONEDA Eric MERCER Chris MYERS 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2002/12/01
Vol. E85-A  No. 12 ; pp. 2684-2692
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis
Keyword: 
logic synthesis, partial order reduction, timed circuits, modular synthesis, 
 Summary | Full Text:PDF