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IEICE Trans

Keyword : structured analysis method

High-Level VLSI Design Specification Validation Using Algorithmic Debugging
Jiro NAGANUMA Takeshi OGURA Tamio HOSHINO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 1988-1998
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
high-level design specification validation, structured analysis method, algorithmic debugging, logic programming languages, 
 Summary | Full Text:PDF