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| Keyword : schedule exploration
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Energy Minimization of Full TMR Design with Optimized Selection of Temporal/Spatial TMR Mode and Supply Voltage
Kazuhito ITO | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2014/12/01
Vol. E97-A
No. 12 ;
pp. 2530-2539
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: High-Level Synthesis and System-Level Design
Keyword:
triple modular redundancy, low energy, MIP, simulated annealing, schedule exploration, | | | Summary | Full Text:PDF | |
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