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IEICE Trans

Keyword : scannable memory configuration

Embedded Memory Array Testing Using a Scannable Configuration
Seiken YANO Nagisa ISHIURA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/10/25
Vol. E80-A  No. 10 ; pp. 1934-1944
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
scannable memory configuration, memory array testing, design-for-testability, scan design, 
 Summary | Full Text:PDF