Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1997/03/25
Vol. E80-A
No. 3 ;
pp. 514-520
Type of Manuscript:
Special Section PAPER (Special Section of Selected Papers from the 9th Karuizawa Workshop on Circuits and Systems)
Category:
Keyword:
design-for-testability, DFT scan design, scannable memory array, memory array testing, |