Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A
No. 12 ;
pp. 2778-2789
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword:
equivalence checking, logic with equality and uninterpreted functions, equivalence constraint, satisfiability checking, |