Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2024/03/01 Vol. E107-ANo. 3 ;
pp. 583-591 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: VLSI Design Technology and CAD Keyword: logic locking, register transfer level, SAT attack, FALL attack, design for security, controller,
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1998/12/25 Vol. E81-ANo. 12 ;
pp. 2646-2654 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Test Keyword: testability analysis, register transfer level, design for testability,