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IEICE Trans

Keyword : reduced scan shift

A Reduced Scan Shift Method for Sequential Circuit Testing
Yoshinobu HIGAMI Seiji KAJIHARA Kozo KINOSHITA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/12/25
Vol. E77-A  No. 12 ; pp. 2010-2016
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: 
Keyword: 
sequential circuit, test generation, design for testability, scan circuit, reduced scan shift, 
 Summary | Full Text:PDF