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IEICE Trans

Keyword : reduced ordered binary decision diagram

Applications of Tree/Link Partitioning for Moment Computations of General Lumped R(L)C Interconnect Networks with Multiple Resistor Loops
Herng-Jer LEE Ming-Hong LAI Chia-Chi CHU Wu-Shiung FENG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2004/12/01
Vol. E87-A  No. 12 ; pp. 3281-3292
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Physical Design
Keyword: 
moment computations, resistor loop, tree/link partition, reduced ordered binary decision diagram, 
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