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IEICE Trans

Keyword : recursive data layout

A Cache Memory with 3-Level Tile-Based Data Layout and Tag-Memory Optimization Method for 2-D Data Access
Baokang WANG Min YU Wenlun ZHANG 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2025/12/01
Vol. E108-A  No. 12 ; pp. 1612-1619
Type of Manuscript:  PAPER
Category: VLSI Design Technology and CAD
Keyword: 
cache memory, tile/line, recursive data layout, 
 Summary | Full Text:PDF