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IEICE Trans

Keyword : random switching logic

A Design Methodology for a DPA-Resistant Circuit with RSL Techniques
Daisuke SUZUKI Minoru SAEKI Koichi SHIMIZU Akashi SATOH Tsutomu MATSUMOTO 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/12/01
Vol. E93-A  No. 12 ; pp. 2497-2508
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis, Test and Verification
Keyword: 
side-channel attacks, differential power analysis, hardware countermeasure, random switching logic, CMOS logic circuit, 
 Summary | Full Text:PDF
On Clock-Based Fault Analysis Attack for an AES Hardware Using RSL
Kazuo SAKIYAMA Kazuo OHTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2010/01/01
Vol. E93-A  No. 1 ; pp. 172-179
Type of Manuscript:  Special Section PAPER (Special Section on Cryptography and Information Security)
Category: Cryptanalysis
Keyword: 
fault analysis, random switching logic, AES, clock-based fault analysis attack, 
 Summary | Full Text:PDF