A Contraction Algorithm Using a Sign Test for Finding All Solutions of Piecewise-Linear Resistive Circuits Kiyotaka YAMAMURAMasakazu MISHINA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1996/10/25 Vol. E79-ANo. 10 ;
pp. 1733-1736 Type of Manuscript: LETTER Category: Nonlinear Problems Keyword: piecewise-linear resistive circuit, all solutions, sign test,
Finding All Solutions of Piecewise-Linear Resistive Circuits Containing Sophisticated Transistor Models Kiyotaka YAMAMURANobuo SEKIGUCHI
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1995/01/25 Vol. E78-ANo. 1 ;
pp. 117-122 Type of Manuscript: PAPER Category: Numerical Analysis and Self-Validation Keyword: piecewise-linear resistive circuit, transistor model, all solutions, separability, sign test,
A Simple Algorithm for Finding All Solutions of Piecewise-Linear Resistive Circuits Kiyotaka YAMAMURA
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 1993/10/25 Vol. E76-ANo. 10 ;
pp. 1812-1821 Type of Manuscript: PAPER Category: Nonlinear Circuits and Systems Keyword: piecewise-linear resistive circuit, all solutions, separability, sign test,