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IEICE Trans

Keyword : phase adjustment

A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver
Fumihiko TACHIBANA Huy CU NGO Go URAKAWA Takashi TOI Mitsuyuki ASHIDA Yuta TSUBOUCHI Mai NOZAWA Junji WADATSUMI Hiroyuki KOBAYASHI Jun DEGUCHI 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2024/05/01
Vol. E107-A  No. 5 ; pp. 709-718
Type of Manuscript:  Special Section PAPER (Special Section on Analog Circuit Techniques and Related Topics)
Category: 
Keyword: 
baud-rate CDR, PAM4, false-lock-aware, phase adjustment, 
 Summary | Full Text:PDF