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IEICE Trans

Keyword : pattern classifier

Analog CMOS Implementation of Quantized Interconnection Neural Networks for Memorizing Limit Cycles
Cheol-Young PARK Koji NAKAJIMA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1999/06/25
Vol. E82-A  No. 6 ; pp. 952-957
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98))
Category: 
Keyword: 
neural network, limit cycles, quantized interconnection, programmable synapse, pattern classifier, 
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