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IEICE Trans

Keyword : partial scan design methods

Novel DFT Strategies Using Full/Partial Scan Designs and Test Point Insertion to Reduce Test Application Time
Toshinori HOSOKAWA Masayoshi YOSHIMURA Mitsuyasu OHTA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2001/11/01
Vol. E84-A  No. 11 ; pp. 2722-2730
Type of Manuscript:  Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Test
Keyword: 
DFT strategies, full scan design methods, partial scan design methods, test point insertions, test application time, 
 Summary | Full Text:PDF