A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG Hideyuki ICHIHARATomoo INOUE
Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences Publication Date: 2003/12/01 Vol. E86-ANo. 12 ;
pp. 3072-3078 Type of Manuscript: Special Section PAPER (Special Section on VLSI Design and CAD Algorithms) Category: Timing Verification and Test Generation Keyword: test generation, acyclic sequential circuits, stuck-at fault, partial scan, multiple fault,