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IEICE Trans

Keyword : parallel signal processing

VLSI Systolic Array for SRIF Digital Signal Processing Algorithm
Kazuhiko IWAMI Koji TANAKA 
Publication:   IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 1994/09/25
Vol. E77-A  No. 9 ; pp. 1475-1483
Type of Manuscript:  Special Section PAPER (Special Section of Papers Selected from the 8th Digital Signal Processing Symposium)
Category: Digital Signal Processing Hardware
Keyword: 
digital signal processing, parallel signal processing, VLSI design technology, 
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