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| Keyword : parallel prefix adder
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Timing-Constrained Area Minimization Algorithm for Parallel Prefix Adders
Taeko MATSUNAGA Yusuke MATSUNAGA | Publication: IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences
Publication Date: 2007/12/01
Vol. E90-A
No. 12 ;
pp. 2770-2777
Type of Manuscript:
Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
Category: Logic Synthesis and Verification
Keyword:
parallel prefix adder, arithmetic synthesis, dynamic programming, | | | Summary | Full Text:PDF | |
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